November 13, 2000 -- 0-In Design Automation, Inc., the industry leader in white-box verification technology, today announced that its new release of the CheckerWare™ library includes a unique method for measuring the effectiveness of simulation testbenches. This metric indicates how well simulations exercise the corner-case behaviors of RTL structural elements, and is the first metric that is directly correlated to bugs. In the new release, each component in 0-In's CheckerWare™ library includes design error detection, simulation activity statistics, and structural coverage.

An Extension of 0-In White-Box Technology
"Structural coverage is one more aspect of 0-In's white-box technology," said 0-In CEO Dr. L. Curtis Widdoes. "0-In's CheckerWare library allows designers to efficiently capture design intent in an executable form. We have extended that basic capability to provide objective, actionable feedback about the thoroughness of the verification test suite, i.e., measurements of how well the testbench exercises the corner-case behaviors of internal RTL design structures."

Corner-Case Analysis Operates on RTL Structures Known to Designers
0-In's structural coverage reports are easy to understand since they reference FIFOs, memories, state machines, interfaces and other structures already understood by the designer. Each of these structures has corner cases that must be exercised as part of a thorough functional verification process. Examples of corner-case behavior reported by 0-In tools include:

• Whether a FIFO has been filled and emptied
• Whether multiple requests have been asserted to an arbiter
• Whether all variations of legal transactions have been run on an interface
• Whether a variable has been set to its legal maximum and minimum values

New Capability Fills Gap in Functional Verification Methodology
"Structural coverage is a much more rigorous measure of testbench efficacy than the metrics that are commonly in use today," said Dr. Widdoes. "Most SOC designs today are verified using metrics such as line coverage, which can bear little correlation to bugs. Measuring corner-case coverage is more useful because a testbench that misses corner cases for RTL structures is almost certain to miss bugs."

Structural Coverage Results Integrate into Existing Verification Environments
0-In Check monitors RTL structures during simulation and produces reports on the level of structural coverage. SOC verification suites typically contain hundreds or thousands of individual simulation tests, and it is critical that the verification regression suite exercise all corner cases of all RTL structures. The 0-In View utility allows structural coverage results from multiple tests to be merged together and viewed as a composite report so that verification engineers can check that the regression suite covers all corner cases.

Products and Pricing
0-In Check is a testbench independent product that supports leading Verilog simulators. 0-In Check is $25,000 at North American List price. The CheckerWare library and the new structural coverage capability are bundled with 0-In Check at no additional charge.

About 0-In
0-In Design Automation, Inc. (pronounced "zero-in") is a privately held electronic design automation (EDA) company that develops tools that zero-in on functional bugs in ASIC and IC designs. 0-In was founded in 1996 and is based in San Jose, CA, with sales offices in Boxborough, MA and Austin, TX plus distribution in Japan through Pacific Design Inc. Leading-edge companies that have adopted 0-In tools and methodologies include AMD, Fujitsu, Hitachi, Hughes, Lucent, Nortel, Sun and Tensilica. More information on 0-In is available at http://www.0-in.com

Contact: Steven D White, 0-In Design Automation, 408-487-3649, swhite@0-in.com